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MIC5891
Micrel
MIC5891
8-Bit Serial-Input Latched Source Driver
General Description
The MIC5891 latched driver is a high-voltage, high current integrated circuit comprised of eight CMOS data latches, CMOS control circuitry for the common STROBE and OUTPUT ENABLE, and bipolar Darlington transistor drivers for each latch. Bipolar/MOS construction provides extremely low power latches with maximum interface flexibility. The MIC5891 will typically operate at 5MHz with a 5V logic supply. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS logic levels. TTL circuits may be used with appropriate pull-up resistors to ensure a proper logic-high input. A CMOS serial data output allows additional drivers to be cascaded when more than 8 bits are required. The MIC5891 has open-emitter outputs with suppression diodes for protection against inductive load transients. The output transistors are capable of sourcing 500mA and will sustain at least 35V in the on-state. Simultaneous operation of all drivers at maximum rated current requires a reduction in duty cycle due to package power limitations. Outputs may be paralleled for higher load current capability. The MIC5891 is available in a 16-pin plastic DIP package (N) and 16-pin wide SOIC package (WM).
Features
* * * * * High-voltage, high-current outputs Output transient protection diodes CMOS-, PMOS-, NMOS-, and TTL-compatible inputs 5MHz typical data input rate Low-power CMOS latches
Applications
* * * * Alphanumeric and bar graph displays LED and incandescent displays Relay and solenoid drivers Other high-power loads
Ordering Information
Part Number MIC5891BN MIC5891BWM Temperature Range -40C to +85C -40C to +85C Package 16-Pin Plastic DIP 16-pin Wide SOIC
Functional Diagram
CLOCK SERIAL DATA IN 8-BIT SERIAL PARALLEL SHIFT REGISTER
Pin Configurations
16 SERIAL DATA OUT
SHIFT VDD 15 LOGIC SUPPLY REGISTER
OE
SERIAL DATA OUT
GROUND CLOCK
1 2 3 4 5 6 7 8
LATCHES
STROBE GROUND
LATCHES OUTPUT ENABLE MOS BIPOLAR
SERIAL DATA IN STROBE OUT1 OUT2 OUT3 OUT4
14
OUTPUT ENABLE
VBB
13 LOAD SUPPLY 12 OUT8 11 OUT7 10 OUT6 9 OUT5
OUT1 OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
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Typical Circuits
VDD
Absolute Maximum Ratings (Notes 1, 2, 3)
Output Voltage (VOUT) .............................................. 50V Logic Supply Voltage Range (VDD) ............... 4.5V to 15V Load Supply Voltage Range (VBB) ................ 5.0V to 50V Input Voltage Range (VIN) ................. -0.3V to VDD+0.3V Continuous Collector Current (IC) ........................ 500mA Package Power Dissipation ............................. see graph Operating Temperature Range (TA) ...... -55C to +125C Storage Temperature Range (TS) ......... -65C to +150C
Note 1: Note 2: Note 3: TA = 25C Derate at the rate of 20mW/C above TA = 25C. Micrel CMOS devices have input-static protection but are susceptible to damage when exposed to extremely high static electrical charges.
IN
Typical Input Circuit
VBB
Allowable Duty Cycles
VOUT
Number of Outputs ON at IOUT = -200 mA 8 7
Max. Allowable Duty Cycles at TA of: 50C 53% 60% 70% 83% 100% 100% 100% 100% 60C 47% 54% 64% 75% 94% 100% 100% 100% 70C 41% 48% 56% 67% 84% 100% 100% 100%
Typical Output Circuit
6 5 4 3
7
PACKAGE POWER DISSIPATION (W)
2.5 2 1.5 1 0.5
Allowable Package Power Dissipation vs. Temp.
2 1
PDIP JA = 60C/W
CerDIP JA = 90C/W
0 25 50 75 100 125 150 AMBIENT TEMPERATURE (C)
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Electrical Characteristics
VBB = 50V, VDD = 5V to 12V; TA = +25C; unless noted.
Limits Characteristic Output Leakage Current Output Saturation Voltage Symbol ICEX VCE(SAT) VBB 50V 50V Test Conditions TA = +25C TA = +85C IOUT = -100mA, TA = +85C IOUT = -225mA, TA = +85C IOUT = -350mA, TA = +85C Output Sustaining Voltage Input Voltage VCE(SUS) VIN(1) VIN(0) Input Current Input Impedance Maximum Clock Frequency Serial Data Output Resistance Turn-On Delay Turnoff Delay Supply Current IIN(1) ZIN fc ROUT tPLH tPHL IBB IDD 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V VDD = 5.0V VDD = 12V Output Enable to Output, IOUT = -350mA Output Enable to Output, IOUT = -350mA all outputs on, all outputs open all outputs off VDD = 5V, all outputs off, inputs = 0V VDD = 12V, all outputs off, inputs = 0V VDD = 5V, one output on, all inputs = 0V VDD = 12V, one output on, all inputs = 0V Diode Leakage Current Diode Forward Voltage IH VF Max Open TA = +25C TA = +85C IF = 350mA
Note 4: Positive (negative) current is defined as going into (coming out of) the specified device pin. Note 5: Operation of these devices with standard TTL may require the use of appropriate pull-up resistors.
Min.
Max. -50 -100 1.8 1.9 2.0
Units A A V V V V V V V A A k k MHz
IOUT = -350mA, L = 2mH VDD = 5.0V VDD = 12V VDD = 5V to 12V VDD = VIN = 5.0V VDD = 12V VDD = 5.0V VDD = 12V
35 3.5 10.5 VSS-0.3 VDD+0.3 VDD+0.3 0.8 50 240 100 50 3.3 20 6.0 2.0 10 10 200 100 200 1.0 3.0 50 100 2.0
k k s s mA A A A mA mA A A V
Timing Conditions
A. B. C. D. E. F. G. H. I. (VDD = 5.0V, Logic Levels are VDD and Ground) Minimum data active time before clock pulse (data set-up time) ........................................................................75ns Minimum data active time after clock pulse (data hold time) ..............................................................................75ns Minimum data pulse width .................................................................................................................................150ns Minimum clock pulse width ...............................................................................................................................150ns Minimum time between clock activation and strobe ..........................................................................................300ns Minimum strobe pulse width ..............................................................................................................................100ns Typical time between strobe activation and output transition .............................................................................1.0s Turnoff delay ................................................................................................................ see Electrical Characteristics Turn-on delay ............................................................................................................... see Electrical Characteristics
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CLOCK A B DATA IN E C STROBE F D
OUTPUT ENABLE G OUTN H I
Timing Conditions
Truth Table
Serial Data Input H L X Shift Register Contents Clock Input I1 H L X P1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... RN-1 RN P1 X
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Latch Contents I1 I2 I3 ... IN-1 In Output Enable I1
Output Content I2 I3 ... IN-1 In
R1 R2 R1 R2 X P2 X P3
... RN-2 RN-1 ... RN-2 RN-1 ... RN-1 RN ... X X ... PN-1 PN
R1 R2 R3
P2 X
P3 ... PN-1 PN X ... X X
L H
P1 P2 P3 ... PN-1 PN L L L... L L
7
Applications Information
Serial data present at the input is transferred into the shift register on the rising edge of the CLOCK input pulse. Additional CLOCK pulses shift data information towards the SERIAL DATA OUTPUT. The serial data must appear at the input prior to the rising edge of the CLOCK input waveform. The 8 bits present in the shift register are transferred to the respective latches when the STROBE is high (serial-toparallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Most applications where the latching feature is not used (STROBE tied high) require the OUTPUT ENABLE input to be high during serial data entry. Outputs are active (controlled by the latch state) when the OUTPUT ENABLE is low. All Outputs are low (disabled) when the OUTPUT ENABLE is high. OUTPUT ENABLE does not affect the data in the shift register or latch.
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